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energy metering ic with on-chip fault and missing neutral detection ADE7761A rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features high accuracy, active energy measurement ic supports iec 62053-21 less than 0.1% error over a dynamic range of 500 to 1 supplies active power on the frequency outputs, f1 and f2 high frequency output cf is intended for calibration and supplies instantaneous active power continuous monitoring of the phase and neutral current allows fault detection in 2-wire distribution systems current channels input level best suited for shunt and current transformer sensors uses the larger of the two currents (phase or neutral) to billeven during a fault condition continuous monitoring of th e voltage and current inputs allows missing neutral detection uses one current input (phase or neutral) to bill when missing neutral is detected two logic outputs (fault and revp) can be used to indicate a potential miswiring, fault, or missing neutral condition direct drive for electromechanical counters and 2-phase stepper motors (f1 and f2) proprietary adcs and dsp provide high accuracy over large variations in environmental conditions and time reference 2.5 v 8% (drift 30 ppm/c typical) with external overdrive capability single 5 v supply, low power general description the ADE7761A is a high accuracy, fault-tolerant, electrical energy measurement ic intended for use with 2-wire distribution systems. the part specifications surpass the accuracy requirements as quoted in the iec 62053-21 standard. the only analog circuitry used on the ADE7761A is in the adcs and reference circuit. all other signal processing (such as multiplication and filtering) is carried out in the digital domain. this approach provides superior stability and accuracy over extremes in environmental conditions and over time. the ADE7761A incorporates a fault detection scheme similar to the ade7751 by continuously monitoring both phase and neutral currents. a fault is indicated when the currents differ by more than 6.25%. the ADE7761A incorporates a missing neutral detection scheme by continuously monitoring the input voltage. when a missing neutral condition is detectedno voltage inputthe ADE7761A continues billing based on the active current signal (see the missing neutral mode section). the missing neutral condition is indicated when the fault pin goes high. the ADE7761A supplies average active power information on the low frequency outputs, f1 and f2. the cf logic output gives instantaneous active power information. the ADE7761A includes a power-supply monitoring circuit on the v dd supply pin. internal phase matching circuitry ensures that the voltage and current channels are matched. an internal no-load threshold ensures that the ADE7761A does not exhibit any creep when there is no load. functional block diagram miscal adc 6 5 v 2p v 2n adc adc 4 3 7 v 1b adc 2 v 1a agnd fault v dd v 1n 2.5v reference internal oscillator missing neutral gain adjust missing neutral detection 9 14 17 10 11 12 b>a a<>b a>b zero crossing detection ADE7761A signal processing block 15 1 8 power supply monitor digital-to-frequency converter 16 18 19 20 f1f2 cf revp s0s1scf dgnd rclkin ref in/out hpf lpf 3k 05040-0-001 pga 13 figure 1.
ADE7761A rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings ............................................................ 5 performance i ssues t hat m ay a ffect b illing a ccuracy ........... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 ter mi nolo g y ...................................................................................... 8 typical performance characteristics ............................................. 9 test circ u it ...................................................................................... 10 operation ......................................................................................... 11 power supply monitor ............................................................... 11 analog inputs ............................................................................. 11 internal oscillator ...................................................................... 12 analog-to-digital conversion .................................................. 13 active power calculation .......................................................... 14 digital-to-frequency conversion ............................................ 16 transfer function ....................................................................... 16 fault detection ........................................................................... 17 missing neutral mode ............................................................... 18 applications ..................................................................................... 21 interfacing to a microcontroller for energy measurement .. 21 selecting a frequency for an energy meter application ...... 21 negative power information ..................................................... 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 7/06revision 0: initial version
ADE7761A rev. 0 | page 3 of 24 specifications v dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, on-chip oscillator, t min to t max = ?40c to +85c. table 1. parameter value unit test conditions/comments accuracy 1 measurement error 2 0.1 % of reading, typ over a dynamic range of 500 to 1 phase error between channels pf = 0.8 capacitive 0.05 degrees, max phase lead 37 pf = 0.5 inductive 0.05 degrees, max phase lag 60 ac power supply rejection 2 output frequency variation 0.01 %, typ v 1a = v 1b = v 2p = 100 mv rms dc power supply rejection 2 output frequency variation 0.01 %, typ v 1a = v 1b = v 2p = 100 mv rms fault detec tion 2 , 3 see the fault detection section fault detection threshold inactive input <> active input 6.25 %, typ v 1a or v 1b active input swap threshold inactive input <> active input 6.25 % of larger, typ v 1a or v 1b active accuracy fault mode operation v 1a active, v 1b = agnd 0.1 % of reading, typ over a dynamic range of 500 to 1 v 1b active, v 1a = agnd 0.1 % of reading, typ over a dynamic range of 500 to 1 fault detection delay 3 seconds, typ swap delay 3 seconds, typ missing neutral mode 2 , 4 see the missing neutral detection section missing neutral detection threshold v 2p ? v 2n 59.4 mv peak, min accuracy missing neutral mode v 1a active, v 1b = v 2p = agnd 0.1 % of reading, typ over a dynamic range of 500 to 1 v 1b active, v 1a = v 2p = agnd 0.1 % of reading, typ over a dynamic range of 500 to 1 missing neutral detection delay 3 seconds, typ analog inputs v 1a ? v 1n , v 1b ? v 1n , v 2p ? v 2n maximum signal levels 660 mv peak, max differential input 660 mv peak, max differential input miscal ? v 2n input impedance (dc) 400 k, min bandwidth (?3 db) 7 khz, typ adc offset error 2 15 mv, typ uncalibrated error, see the terminology section for details gain error 4 %, typ external 2.5 v reference gain error match 2 3 %, typ external 2.5 v reference reference input ref in/out input voltage range 2.7 v, max 2.5 v + 8% 2.3 v, min 2.5 v ? 8% input impedance 3 k, min input capacitance 10 pf, max on-chip reference reference error 200 mv, max temperature coefficient 30 ppm/c, typ current source 20 a, min on-chip oscillator oscillator frequency 450 khz oscillator frequency tolerance 12 % of reading, typ temperature coefficient 30 ppm/c, typ
ADE7761A rev. 0 | page 4 of 24 parameter value unit test conditions/comments logic inputs 5 pga, scf, s1, and s0 input high voltage, v inh 2.4 v, min v dd = 5 v 5% input low voltage, v inl 0.8 v, max v dd = 5 v 5% input current, i in 3 a, max typical 10 na, v in = 0 v to v dd input capacitance, c in 10 pf, max logic outputs 5 cf, revp, and fault output high voltage, v oh 4 v, min v dd = 5 v 5% output low voltage, v oh 1 v, max v dd = 5 v 5% f1 and f2 output high voltage, v oh 4 v, min v dd = 5 v 5%, i source = 10 ma output low voltage, v oh 1 v, max v dd = 5 v 5%, i sink = 10 ma power supply for specified performance v dd 4.75 v, min 5 v ? 5% 5.25 v, max 5 v + 5% v dd 3 ma, max 1 see plots in the typical performance characteristics section. 2 see the terminology section for explanation of specifications. 3 see the fault detection section for explanation of fault detection functionality. 4 see the missing neutral detection section for explanation of missing neutral detection functionality. 5 sample tested during initial release and after any redesign or process change that might affect this parameter. timing characteristics v dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, on-chip oscillator, t min to t max = ?40c to +85c. sample tested during initial release and after any redesign or process change that might affect this parameter. see figure 2 . table 2. parameter value unit test conditions/comments t 1 1 120 ms f1 and f2 pulse width (logic high). t 2 see table 7 s output pulse period. see the transfer function section. t 3 1/2 t 2 s time between f1 falling edge and f2 falling edge. t 4 1 90 ms cf pulse width (logic high). t 5 see table 8 s cf pulse period. see the transfer function section. t 6 clkin/4 s minimum time between f1 and f2 pulse. 1 the pulse widths of f1, f2, and cf ar e not fixed for higher output frequencies. see the transfer function section. t 1 t 6 t 3 t 4 t 2 t 5 f1 f2 cf 05040-002 figure 2. timing diagram for frequency outputs
ADE7761A rev. 0 | page 5 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to agnd ?0.3 v to +7 v analog input voltage to agnd v 1a , v 1b , v 1n , v 2n , v 2p , miscal ?6 v to +6 v reference input voltage to agnd ?0.3 v to v dd + 0.3 v digital input voltage to dgnd ?0.3 v to v dd + 0.3 v digital output voltage to dgnd ?0.3 v to v dd + 0.3 v operating temperature range industrial ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c 20-lead ssop, power dissipation 450 mw ja thermal impedance 112c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. performance issues that may affect billing accuracy the ADE7761A provides pulse outputscf, f1, and f2 intended to be used for the billing of active energy. pulses are generated at these outputs in two different situations. case 1 : when the analog input v 2p C v 2n complies with the conditions described in figure 34 , cf, f1, and f2 frequencies are proportional to active power and can be used to bill active energy. case 2 : when the analog input v 2p C v 2n does not comply with the conditions described in figure 34 , the ADE7761A does not measure active energy but a quantity proportional to kah. this quantity is used to generate pulses on the same cf, f1, and f2. this situation is indicated when the fault pin is high. analog devices, inc. cautions users of the ADE7761A about the following: ? billing active energy in case 1 is consistent with the understanding of the quantity represented by pulses on cf, f1, and f2 outputs (watt-hour). ? billing active energy while the ADE7761A is in case 2 must be decided knowing that the entity measured by the ADE7761A in this case is ampere-hour and not watt-hour. users should be aware of this limitation and decide if the ADE7761A is appropriate for their application. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ADE7761A rev. 0 | page 6 of 24 pin configuration and fu nction descriptions ref in/out s0 scf s1 v dd f1 v 1a f2 v 1b cf v 1n dgnd v 2n revp v 2p fault miscal rclkin agnd pga 1 2 3 4 20 19 18 17 5 6 7 16 15 14 8 13 9 12 10 11 ADE7761A top view (not to scale) 05040-003 figure 3. pin configuration (ssop) table 4. pin function descriptions pin no. mnemonic description 1 v dd power supply. this pin provides the supply voltage for the digital circuitry in the ADE7761A. the supply voltage should be maintained at 5 v 5% for specified operation . this pin should be decoupled with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 2, 3 v 1a , v 1b analog inputs for channel 1 (current channel). these inp uts are fully differential voltage inputs with maximum differential input signal levels of 660 mv with respect to v 1n for specified operation. the maximum signal level at these pins is 1 v with respect to agnd. both inputs have internal esd prot ection circuitry, and an overvoltage of 6 v can also be sustained on these in puts without risk of permanent damage. 4 v 1n negative input for differential voltage inputs, v 1a and v 1b . the maximum signal level at this pin is 1 v with respect to agnd. the input has internal esd protection circui try, and an overvoltage of 6 v can also be sustained on this input without risk of permanent damage. the input should be directly connected to the burden resistor and held at a fixed potential, that is, agnd. see the analog inputs section. 5 v 2n negative input for differential voltage inputs, v 2p and miscal. the maximum signal level at this pin is 1 v with respect to agnd. the input has internal esd protection circui try, and an overvoltage of 6 v can also be sustained on this input without risk of permanent damage. the input should be held at a fixed potential, that is, agnd. see the analog inputs section. 6 v 2p analog input for channel 2 (voltage channel). this inp ut is a fully differential voltage input with maximum differential input signal levels of 660 mv with respect to v 2n for specified operation. the maximum signal level at this pin is 1 v with respect to agnd. this input has intern al esd protection circuitry, and an overvoltage of 6 v can also be sustained on this inp ut without risk of permanent damage. 7 miscal analog input for missing neutral calibration. this pin ca n be used to calibrate the cf-f1-f2 frequencies in the missing neutral condition. this input is a fully differenti al voltage input with maximum differential input signal levels of 660 mv with respect to v 2n for specified operation. the maximum signal level at this pin is 1 v with respect to agnd. this input has internal esd protection circuitry, and an overvoltage of 6 v can also be sustained on this input witho ut risk of permanent damage. 8 agnd this pin provides the ground reference for the analog circ uitry in the ADE7761A, that is, adcs and reference. this pin should be tied to the analog ground plane of the pcb. the analog ground plane is the ground reference for all analog circuitry, such as antialiasing filters, and curren t and voltage transducers. for good noise suppression, the analog ground plane should be connected only to the digital ground plane at the dgnd pin. 9 ref in/out this pin provides access to the on-chip voltage reference. the on-chip reference has a nominal value of 2.5 v 8% and a typical temperature coefficient of 30 ppm/c. an external reference source can also be connected at this pin. in either case, this pin should be decoupled to agnd with a 1 f ceramic capacitor and 100 nf ceramic capacitor. 10 scf select calibration frequency. this logic input is used to select the frequency on the calibration output cf. table 7 shows how the calibration frequencies are selected. 11, 12 s1, s0 these logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion. this offers the designer greater flexibility when designing the energy meter. see the selecting a frequency for an energy meter application section. 13 pga this logic input is used to sele ct the gain for the analog inputs, v 1a and v 1b . the possible gains are 1 and 16. 14 rclkin to enable the internal oscillator as a clock source on the chip, a precise low temperature drift resistor at nominal value of 6.2 k must be connected from this pin to dgnd.
ADE7761A rev. 0 | page 7 of 24 pin no. mnemonic description 15 fault this logic output goes active high when a fault or missi ng neutral condition occurs. a fault is defined as a condition under which the signals on v 1a and v 1b differ by more than 6.25%. a missing neutral condition is defined when the chip is powered up with no voltage at th e input. the logic output is re set to zero when a fault or missing neutral condition is no longer detected. see the fault detection section and the missing neutral mode section. 16 revp this logic output goes logic high when negative power is detected, that is, when the phase angle between the voltage and current signals is greater than 90. this output is not latched and is reset when positive power is once again detected. the output goes high or low at the same time as a pulse is issued on cf. 17 dgnd this pin provides the ground reference for the digital circ uitry in the ADE7761A, that is, multiplier, filters, and digital-to-frequency converters. this pin should be tied to the digital ground plane of the pcb. the digital ground plane is the ground reference for all digital circuitry, such as counters (mechanical and digital), mcus, and indicator leds. for good noise suppression, the analog gr ound plane should be connected only to the digital ground plane at the dgnd pin. 18 cf calibration frequency logic output. the cf logic output, active high, gives instantaneous active power information. this output is used for opera tional and calibration purposes. see the digital-to-frequency conversion section. 19, 20 f2, f1 low frequency logic outputs. f1 and f2 supply average active power information. the logic outputs can be used to directly drive electromechanical counters and 2-phase stepper motors.
ADE7761A rev. 0 | page 8 of 24 terminology measurement error the error associated with the energy measurement made by the ADE7761A is defined by ? ? ? ? ? ? ? ? ? = %100 energytrue energytrue ADE7761A byregistered energy erro r percentag e phase error between channels the high-pass filter (hpf) in the current channel has a phase lead response. to offset this phase response and equalize the phase response among channels, a phase correction network is also placed in the current channel. the phase correction network ensures a phase match between the current channels and voltage channels to within 0.1 over a range of 45 hz to 65 hz and 0.2 over a range of 40 hz to 1 khz. power supply rejection (psr) psr quantifies the ADE7761A measurement error as a percentage of reading when the power supplies are varied. for the ac psr measurement, a reading at nominal supplies (5 v) is taken. a second reading is obtained with the same input signal levels when an ac (175 mv rms/100 hz) signal is introduced onto the supplies. any error introduced by this ac signal is expressed as a percentage of reading (see the measurement error definition). for the dc psr measurement, a reading at nominal supplies (5 v) is taken. a second reading is obtained with the same input signal levels when the power supplies are varied 5%. any error introduced is again expressed as a percentage of reading. adc offset error the dc offset associated with the analog inputs to the adcs. with the analog inputs connected to agnd, the adcs still see a dc analog input signal. the magnitude of the offset depends on the input gain and range selection (see the typical performance characteristics section). however, when hpfs are switched on, the offset is removed from the current channels and the power calculation is not affected by this offset. gain error the gain error in the ADE7761A adcs is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. it is measured with a gain of 1 in channel v 1a . the difference is expressed as a percentage of the ideal frequency, which is obtained from the transfer function (see the transfer function section). gain error match the gain error match is defined as the gain error (minus the offset) obtained when switching be tween a gain of 1 or 16. it is expressed as a percentage of the output adc code obtained under a gain of 1.
ADE7761A rev. 0 | page 9 of 24 typical performance characteristics 05040-004 current (% of full scale) 100.0 0.1 1.0 10.0 % error ?1.0 1.0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 0 ?0.6 ?0.8 pf = 1 on-chip reference ?40c +25c +85c figure 4. active power error as a percentage of reading with gain = 1 and internal reference 05040-005 current (% of full scale) 100 0.1 1.0 10 % error ?1.0 1.5 1.0 0.5 0 ?0.5 pf = different values on-chip reference ?40c; pf = 0.5 +25c; pf = 1 +25c; pf = 0.5 +85c; pf = 0.5 figure 5. active power error as a percentage of reading over power factor with gain = 1 and internal reference ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.10 1 10 100 current (% full scale) % erro r 05040-034 +25c +85c ?40c 0.6 0.8 1.0 pf = 1. gain = 16 on-chip reference figure 6. active power error as a percentage of reading with gain = 16 and internal reference ?0.2 0 0.2 0.4 0.10 1 10 100 current (% full scale) % erro r 0.6 gain = 16 on-chip reference 05040-035 pf = ?0.5 pf = +1 pf = +0.5 1.0 0.8 ?0.8 ?0.6 ?0.4 ?1.0 figure 7. active power error as a percentage of reading over power factor with gain = 16 and internal reference 05040-006 current (% of full scale) 100.0 0.1 1.0 10.0 % error ?1.0 1.0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 0 ?0.6 ?0.8 pf = 1 on-chip reference 5.25v 5.00v 4.75v figure 8. active power error as a percentage of reading over power supply with gain = 1 and internal reference 05040-007 current (% of full scale) 100.0 0.1 1.0 10.0 % error ?2.0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 on-chip reference +85c +25c ?40c figure 9. ampere hour error as a percentage of reading in missing neutral mode with gain = 1 and internal reference
ADE7761A rev. 0 | page 10 of 24 test circuit v dd ref in/out 100nf 10f v dd agnd dgnd pga cf fault rclkin s1 scf ps2501-1 ADE7761A to freq. counter v 1a v 1b v 1n 100nf 10f v 2n i 33nf 1k ? s0 6.2k ? 10k ? 40a to 80ma rb = 18 ? 1 18 15 14 12 11 10 9 17 13 8 5 4 3 2 + 2k ? 2k ? 1 2 v 2p miscal 33nf 1k ? 1m ? 220 v 6 7 100k ? 560k ? 33nf 33nf 1k ? rb 33nf 1k ? rb 33nf 1k ? + 3 4 05040-008 figure 10. test circuit for performance curves
ADE7761A rev. 0 | page 11 of 24 operation power supply monitor the ADE7761A continuously monitors the power supply (v dd ) with its on-chip, power supply monitor. if the supply is less than 4 v 5%, the ADE7761A goes into an inactive state, that is, no energy is accumulated and the cf, f1, and f2 outputs are disabled. this is useful to ensure correct device operation at power-up and during power-down. the power supply monitor has built-in hysteresis and filtering, which provides a high degree of immunity to false triggering due to noisy supplies. the power supply and decoupling for the part should be such that the ripple at v dd does not exceed 5 v 5% as specified for normal operation. ADE7761A revp - fault - cf - f1 - f2 outputs inactive active time inactive v dd 5v 4v 0v 05040-009 figure 11. on-chip, po wer supply monitoring analog inputs channel v1 (current channel) the voltage outputs from the current transducers are connected to the ADE7761A at channel v1. it has two voltage inputs, v 1a and v 1b . these inputs are fully differential with respect to v 1n . however, at any one time, only one is selected to perform the power calculation (see the fault detection section). the maximum peak differential signal on v 1a ? v 1n and v 1b ? v 1n is 660 mv. however, channel 1 has a programmable gain amplifier (pga) with user-selectable gains of 1 or 16 (see table 5 ). this gain facilitates easy transducer interfacing. table 5. channel 1 dynamic range pga gain maximum differential signal (mv) 0 1 660 1 16 41 figure 12 shows the maximum signal levels on v 1a , v 1b , and v 1n . the maximum differential voltage is 660 mv divided by the gain selection. the differential voltage signal on the inputs must be referenced to a common mode (usually agnd). v cm differential input b 660mv max peak v 1b v 1n v 1a v1 v1 v cm common mode 100mv max differential input a 660mv max peak agnd v 1a , v 1b 05040-010 +660mv gain ?660mv gain + v cm + v cm figure 12. maximum signal levels, channel 1 channel v2 (voltage channel) the output of the line voltage transducer is connected to the ADE7761A at this analog input. channel v2 is a single-ended, voltage input. the maximum peak differential signal on channel 2 is 660 mv with respect to v 2n . figure 13 shows the maximum signal levels that can be connected to channel 2. 05040-011 v cm +660mv + v cm ?660mv + v cm common mode 100mv max v 2n v 2p v cm v2 differential input 660mv max peak v 2 figure 13. maximum signal levels, channel 2 the differential voltage v 2p ? v 2n must be referenced to a common mode (usually agnd). the analog inputs of the ADE7761A can be driven with common-mode voltages of up to 100 mv with respect to agnd. however, the best results are achieved using a common mode equal to agnd. miscal input the input for the power calibration in missing neutral mode is connected to the ADE7761A at this analog input. miscal is a single-ended, voltage input. it is recommended to use a dc signal derived from the voltage reference to drive this pin. the maximum peak differential signal on miscal is 660 mv with respect to v 2n . figure 14 shows the maximum signal levels that can be connected to the miscal pin. 05040-012 v cm +660mv + v cm common mode 100mv max v 2n miscal v cm miscal differential input 660mv max peak miscal agnd figure 14. maximum signal levels, miscal
ADE7761A rev. 0 | page 12 of 24 the differential voltage miscal ? v 2n must be referenced to a common mode (usually agnd). the analog inputs of the ADE7761A can be driven with common-mode voltages of up to 100 mv with respect to agnd. however, best results are achieved using a common mode equal to agnd. typical connection diagrams figure 15 shows a typical connection diagram for channel v1. the analog inputs are used to monitor both the phase and neutral currents. because of the large potential difference between the phase and neutral, two current transformers (cts) must be used to provide the isolation. note that both cts are referenced to analog ground (agnd); therefore, the common- mode voltage is 0 v. the ct turns ratio and burden resistor (rb) are selected to give a peak differential voltage of 660 mv/gain. agnd v 1b v 1n v 1a r f r f c f c f ct ct rb rb in ip phase neutral 05040-013 660mv gain 660mv gain figure 15. typical connection for channel 1 figure 16 shows two typical connections for channel v2. the first option uses a potential transformer (pt) to provide complete isolation from the main voltage. in the second option, the ADE7761A is biased around the neutral wire, and a resistor divider is used to provide a voltage signal that is proportional to the line voltage. adjusting the ratio of ra and rb + vr is a convenient way to carry out a gain calibration on the meter. 05040-014 1 rb + vr = rf. vr 1 rb 1 ra 1 v 2p neutral phase r f v 2n c t v 2p neutral phase r f r f v 2n c f c f c f 660mv agnd figure 16. typical connection for channel 2 figure 17 shows a typical connection for the miscal input. the voltage reference input (ref in/out ) is used as a dc reference to set the miscal voltage. adjusting the level of miscal to calibrate the meter in missing neutral mode can be done by changing the ratio of rc and rd + vr1. when the internal reference is used, the values of rc, rd, and vr1 must be chosen to limit the current sourced by the internal reference sourcing current to below the specified 20 a. therefore, because v ref internal = 2.5 v, rc + rd + vr1 > 600 k. 05040-015 vr1 rd rc miscal r f v 2n c f c f ref in/out figure 17. typical connection for miscal internal oscillator the nominal internal oscillator frequency is 450 khz when used with the recommended r osc resistor value of 6.2 k between rclkin and dgnd (see figure 18 ). the internal oscillator frequency is inversely proportional to the value of this resistor. although the internal oscillator operates when used with an r osc resistor value between 5 k and 12 k, it is recommended to choose a value within the range of the nominal value. the output frequencies on cf, f1, and f2 are directly propor- tional to the internal oscillator frequency; therefore, the resistor r osc must have a low tolerance and low temperature drift. a low tolerance resistor limits the variation of the internal oscillator frequency. a small variation of the clock frequency and consequently of the output frequencies from meter to meter contributes to a smaller calibration range of the meter. a low temperature drift resistor directly limits the variation of the internal clock frequency over temperature. the stability of the meter to external variation is then better ensured by design. 2.5v reference internal oscillator 9 a de7761 a dgnd rclkin ref in/out 3k ? 05040-016 r osc 14 17 figure 18. internal oscillator connection
ADE7761A rev. 0 | page 13 of 24 analog-to-digital conversion the analog-to-digital conversion in the ADE7761A is carried out using second-order, - adcs. figure 19 shows a first- order, - adc (for simplicity). the converter is made up of two parts: the - modulator and the digital low-pass filter. 04407-017 ....1 0100101 .... 1-bit dac latched compar- ato r integrator v ref mclk c r analog low-pass filter digital low-pass filter 1 24 figure 19. first-order, - adc a - modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. in the ADE7761A, the sampling clock is equal to clkin. the 1-bit dac in the feedback loop is driven by the serial data stream. the dac output is subtracted from the input signal. if the loop gain is high enough, the average value of the dac output (and, therefore, the bit stream) approaches that of the input signal level. for any given input value in a single sampling interval, the data from the 1-bit adc is virtually meaningless. only when a large number of samples are averaged is a meaningful result obtained. this averaging is carried out in the second part of the adc, the digital low-pass filter. by averaging a large number of bits from the modulator, the low-pass filter can produce 24-bit data-words that are proportional to the input signal level. the - converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. the first is oversampling, which means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. for example, the sampling rate in the ADE7761A is clkin (450 khz) and the band of interest is 40 hz to 1 khz. oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. with the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered (see figure 20 ). however, oversampling alone is not an efficient enough method to improve the signal-to-noise ratio (snr) in the band of interest. for example, an oversampling ratio of 4 is required just to increase the snr by only 6 db (1 bit). to keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. this is what happens in the - modulator; the noise is shaped by the integrator, which has a high-pass type response for the quantization noise. the result is that most of the noise is at the higher frequencies, where it can be removed by the digital low- pass filter. this noise shaping is also shown in figure 20 . shaped noise high resolution output from digital lfp noise sign a l noise sign a l 0 1 225 450 frequency (khz) 0 1 225 450 frequency (khz) digital filter a ntialias filter (rc) sampling frequency 05040-018 figure 20. noise reduction due to oversampling and noise shaping in the analog modulator antialias filter figure 20 also shows an analog low-pass filter (rc) on input to the modulator. this filter is present to prevent aliasing. aliasing is an artifact of all sampled systems, which means that frequency components in the input signal to the adc that are higher than half the sampling rate of the adc appear in the sampled signal frequency below half the sampling rate. figure 21 illustrates the effect. in figure 21 , frequency components (arrows shown in black) above half the sampling frequency (also known as the nyquist frequency), that is, 225 khz, are imaged or folded back down below 225 khz (arrows shown in gray). this happens with all adcs no matter what the architecture. in the example shown, only frequencies near the sampling frequency (450 khz) move into the band of interest for metering (40 hz to 1 khz). this fact allows the use of a very simple low-pass filter to attenuate these frequencies (near 250 khz) and thereby prevent distortion in the band of interest. a simple rc filter (single pole) with a corner frequency of 10 khz produces an attenuation of approximately 33 db at 450 khz (see figure 21 ). this is sufficient to eliminate the effects of aliasing. 05040-019 0 1 225 450 frequency (khz) image frequencies sampling frequency a ntialiasing effects figure 21. adc and signal processing in current channel or voltage channel
ADE7761A rev. 0 | page 14 of 24 active power calculation the adcs digitize the voltage signals from the current and voltage transducers. a high-pass filter in the current channel removes any dc component from the current signal. this eliminates any inaccuracies in the active power calculation due to offsets in the voltage or current signals (see the hpf and offset effects section). the active power calculation is derived from the instantaneous power signal. the instantaneous power signal is generated by a direct multiplication of the current and voltage signals. to extract the active power component (dc component), the instantaneous power signal is low-pass filtered. figure 22 illustrates the instantaneous active power signal and shows how the active power information can be extracted by low-pass filtering the instantaneous power signal. this scheme correctly calculates active power for nonsinusoidal current and voltage waveforms at all power factors. all signal processing is carried out in the digital domain for superior stability over temperature and time. 05040-020 f2 cf f1 digital-to- frequency digital-to- frequency hpf multiplier lpf adc adc ch1 ch2 instantaneous power signal ?p(t) instantaneous active power signal v i v i 2 time p(t) = i(t).v(t) where: v(t) = v cos( t) i(t) = i cos( t) p(t) = v i {1 + cos (2 t)} 2 pga figure 22. signal processing block diagram the low frequency output of the ADE7761A is generated by accumulating this active power information. this low frequency inherently means a long accumulation time between output pulses. the output frequency is, therefore, proportional to the average active power. this average active power information can, in turn, be accumulated (for example, by a counter) to generate active energy information. because of its high output frequency and, therefore, shorter integration time, the cf output is proportional to the instantaneous active power. this is useful for system calibration purposes that take place under steady load conditions. power factor considerations the method used to extract the active power information from the instantaneous power signal (by low-pass filtering) is still valid even when the voltage and current signals are not in phase. figure 23 displays the unity power factor condition and a displacement power factor (dpf = 0.5), that is, current signal lagging the voltage by 60. inst a nt a neous power signal instant a neous active power signal instantaneous power signal instantaneous active power signal 60 current current voltage 0v 0v voltage 05040-021 v i 2 v i 2 cos(60) figure 23. active power calculation over pf if one assumes that the voltage and current waveforms are sinusoidal, the active power component of the instantaneous power signal (dc term) is given by ( v i /2) cos(60) this is the correct active power calculation. nonsinusoidal voltage and current the active power calculation method also holds true for nonsinusoidal current and voltage waveforms. all voltage and current waveforms in practical applications have some harmonic content. using the fourier transform, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content ) sin( 2)( 0 h h h o thv vtv duu f z (1) where: v(t) is the instantaneous voltage. v o is the average value. v h is the rms value of voltage harmonic h. h is the phase angle of the voltage harmonic.
ADE7761A rev. 0 | page 15 of 24 ) sin( 2)( 0 h h h o thi iti +?+= (2) where: i(t) is the instantaneous current. i o is the dc component. i h is the rms value of current harmonic h. h is the phase angle of the current harmonic. using equation 1 and equation 2, the active power p can be expressed in terms of its fundamental active power (p 1 ) and harmonic active power (p h ). p = p 1 + p h where: p 1 = v 1 i 1 cos( 1 ) 1 = 1 ? 1 (3) and )cos( 2 = ?= h h hh h ivp hhh ?= (4) as can be seen in equation 4, a harmonic active power component is generated for every harmonic provided that the harmonic is present in both the voltage and current waveforms. the power factor calculation was previously shown to be accurate in the case of a pure sinusoid; therefore, the harmonic active power must also correctly account for the power factor because it is made up of a series of pure sinusoids. note that the input bandwidth of the analog inputs is 7 khz with an internal oscillator frequency of 450 khz. hpf and offset effects equation 5 shows the effect of offsets on the active power calculation. figure 24 shows the effect of offsets on the active power calculation in the frequency domain. )cos( )cos( 2 ))cos( ())cos( ( )()( tivtiv iv iv tiitvv titv 01 10 11 10 10 10 ?+?+ + =?+?+ = (5) as can be seen in equation 5 and figure 24 , an offset on channel 1 and channel 2 contributes a dc component after multiplication. because this dc component is extracted by the lpf and used to generate the active power information, the offsets contribute a constant error to the active power calculation. this problem is easily avoided in the ADE7761A with the hpf in channel 1. by removing the offset from at least one channel, no error component can be generated at dc by the multiplication. error terms at cos( t ) are removed by the lpf and the digital-to-frequency conversion (see the digital-to-frequency conversion section). the hpf in channel 1 has an associated phase response that is compensated for on-chip. figure 25 and figure 26 show the phase error between channels with the compensation network activated. the ADE7761A is phase compensated up to 1 khz as shown, which ensures a correct active harmonic power calculation even at low power factors. 05040-022 dc component (including error term) is extracted by the lpf for active power calculation 2 & frequency (rad/s) 0 ? v 1 i 0 v 0 i 1 v 1 i 1 2 figure 24. effect of channel offsets on the active power calculation frequency (hz) 0 100 phase (degrees) ?0.05 ?0.10 0 0.05 0.10 0.15 0.20 0.25 0.30 200 300 400 500 600 700 800 900 1000 05040-023 figure 25. phase error between channels (0 hz to 1 khz) frequency (hz) 40 phase (degrees) ?0.05 ?0.10 0.05 0 0.10 0.15 0.20 0.25 0.30 45 50 55 60 65 70 05040-024 figure 26. phase error between channels (40 hz to 70 hz)
ADE7761A rev. 0 | page 16 of 24 digital-to-frequency conversion as previously described, the digital output of the low-pass filter after multiplication contains the active power information. however, because this lpf is not an ideal brick wall filter implementation, the output signal also contains attenuated components at the line frequency and its harmonics, that is, cos( h t ), where h = 1, 2, 3, , and so on. the magnitude response of the filter is given by 2 )hz5.4/(1 1 )( f fh = = (6) for a line frequency of 50 hz, this gives an attenuation of the 2 (100 hz) component of approximately ?26.9 db. the dominating harmonic is at twice the line frequency, cos(2 t ), due to the instantaneous power signal. f1 f2 cf digital-to- frequency digital-to- frequency multiplier lpf v i 0 & 2 & frequency (rad/s) lpf to extract active power (dc term) time time 05040-025 frequency frequency f1 fout instantaneous active power signal (frequency domain) figure 27. active power to frequency conversion figure 27 shows the instantaneous active power signal output of the lpf, which still contains a significant amount of instantaneous power information, cos(2 t ). this signal is then passed to the digital-to-frequency converter, where it is integrated (accumulated) over time to produce an output frequency. this accumulation of the signal suppresses or averages out any non-dc components in the instantaneous active power signal. the average value of a sinusoidal signal is zero. therefore, the frequency generated by the ADE7761A is proportional to the average active power. figure 27 also shows the digital-to-frequency conversion for steady load conditions: constant voltage and current. as can be seen in figure 27 , the frequency output cf varies over time, even under steady load conditions. this frequency variation is primarily due to the cos(2 t ) component in the instantaneous active power signal. the output frequency on cf can be up to 2048 times higher than the frequency on f1 and f2. this higher output frequency is generated by accumulating the instantaneous active power signal over a much shorter time while converting it to a frequency. this shorter accumulation period means less averaging of the cos(2 t ) component. as a consequence, some of this instantaneous power signal passes through the digital-to-frequency conversion. this is not a problem in the application. where cf is used for calibration purposes, the frequency should be averaged by the frequency counter, which removes any ripple. if cf is being used to measure energy, such as in a microprocessor-based application, the cf output should also be averaged to calculate power. because the outputs, f1 and f2, operate at a much lower frequency, a lot more averaging of the instantaneous active power signal is carried out. the result is a greatly attenuated sinusoidal content and a virtually ripple-free frequency output. transfer function frequency outputs f1 and f2 the ADE7761A calculates the product of two voltage signals (on channel 1 and channel 2) and then low-pass filters this product to extract active power information. this active power information is then converted to a frequency. the frequency information is output on f1 and f2 in the form of active high pulses. the pulse rate at these outputs is relatively low, for example, 0.34 hz maximum for ac signals with s0 = s1 = 0 (see table 8 ). this means that the frequency at these outputs is generated from active power information accumulated over a relatively long period. the result is an output frequency that is proportional to the average active power. the averaging of the active power signal is implicit to the digital-to-frequency conversion. the output frequency or pulse rate is related to the input voltage signals by 2 21 70.5 ref 41rms rms v fv2v1gain frequency ff ? = ? (7) where: f 1 ? f 2 frequency is the output frequency on f 1 and f 2 (hz). v1 rms is the differential rms voltage signal on channel 1 (v). v2 rms is the differential rms voltage signal on channel 2 (v). gain is 1 or 16, depending on the pga gain selection made using the logic input pga. v ref is the reference voltage (2.5 v 8%) (v). f 1C4 is one of four possible frequencies selected by using the logic inputs s0 and s1 (see tabl e 6 ).
ADE7761A rev. 0 | page 17 of 24 table 6. f 1C4 frequency selection s1 s0 f 1C4 (hz) 1 f 1?4 = osc/2 n 2 0 0 1.72 osc/2 18 0 1 3.44 osc/2 17 1 0 6.86 osc/2 16 1 1 13.7 osc/2 15 1 values are generated using the nominal frequency of 450 khz. 2 f 1C4 are a binary fraction of the master clock and, therefore, vary with the internal oscillator frequency (osc). frequency output cf the pulse output calibration frequency (cf) is intended for use during calibration. the output pulse rate on cf can be up to 2048 times the pulse rate on f1 and f2. the lower the f 1C4 frequency selected, the higher the cf scaling. table 7 shows how the two frequencies are related, depending on the states of the logic inputs s0, s1, and scf. because of its relatively high pulse rate, the frequency at this logic output is proportional to the instantaneous active power. as with f1 and f2, the frequency is derived from the output of the low-pass filter after multiplication. however, because the output frequency is high, this active power information is accumulated over a much shorter time. therefore, less averaging is carried out in the digital-to-frequency conversion. with much less averaging of the active power signal, the cf output is much more responsive to power fluctuations (see figure 22 ). table 7. relationship between cf and f1, f2 frequency outputs scf s1 s0 f 1C4 (hz) cf frequency output 1 0 0 1.72 128 f1, f2 0 0 0 1.72 64 f1, f2 1 0 1 3.44 64 f1, f2 0 0 1 3.44 32 f1, f2 1 1 0 6.86 32 f1, f2 0 1 0 6.86 16 f1, f2 1 1 1 13.7 16 f1, f2 0 1 1 13.7 2048 f1, f2 example in this example, if ac voltages of 660 mv peak are applied to v1 and v2, then the expected output frequency on cf, f1, and f2 is calculated as gain = 1, pga = 0 f 1C4 = 1.7 hz, scf = s1 = s0 = 0 v1 rms = rms of 660 mv peak ac = 0.66/2 v v2 rms = rms of 660 mv peak ac = 0.66/2 v v ref = 2.5 v (nominal reference value) note that if the on-chip reference is used, actual output frequencies can vary from device to device due to a reference tolerance of 8%. hz34.0 5.222 hz72.166.066.070.5 2 21 = = ? cf frequency = f 1 ? f 2 64 = 22.0 hz as can be seen from these two example calculations, the maximum output frequency for ac inputs is always half of that for dc input signals. table 8 shows a complete listing of all maximum output frequencies for ac signals. table 8. maximum output frequencies on cf, f1, and f2 for ac inputs scf s1 s0 f1, f2 maximum frequency (hz) cf maximum frequency (hz) cf-to- f1 ratio 1 0 0 0.34 43.52 128 0 0 0 0.34 21.76 64 1 0 1 0.68 43.52 64 0 0 1 0.68 21.76 32 1 1 0 1.36 43.52 32 0 1 0 1.36 21.76 16 1 1 1 2.72 43.52 16 0 1 1 2.72 5570 2048 fault detection the ADE7761A incorporates a novel fault detection scheme that warns of fault conditions and allows the ADE7761A to continue accurate billing during a fault event. the ADE7761A does this by continuously monitoring both the phase and neutral (return) currents. a fault is indicated when these currents differ by more than 6.25%. however, even during a fault, the output pulse rate on f1 and f2 is generated using the larger of the two currents. because the ADE7761A looks for a difference between the voltage signals on v 1a and v 1b , it is important that both current transducers be closely matched. on power-up, the output pulse rate of the ADE7761A is proportional to the product of the voltage signals on v 1a and channel 2. if the difference between v 1a and v 1b on power-up is greater than 6.25%, the fault indicator (fault) becomes active after about 1 sec. in addition, if v 1b is greater than v 1a , the ADE7761A selects v 1b as the input. the fault detection is automatically disabled when the voltage signal on channel 1 is less than 0.3% of the full-scale input range. this eliminates false detection of a fault due to noise at light loads.
ADE7761A rev. 0 | page 18 of 24 fault with active input greater than inactive input if v 1a is the active current input (that is, being used for billing), and the voltage signal on v 1b (inactive input) falls below 93.75% of v 1a , the fault indicator becomes active. both analog inputs are filtered and averaged to prevent false triggering of this logic output. as a consequence of the filtering, there is a time delay of approximately 3 sec on the logic output fault after the fault event. the fault logic output is independent of any activity on outputs f1 or f2. figure 28 shows one condition under which fault becomes active. because v 1a is the active input and it is still greater than v 1b , billing is maintained on v 1a , that is, no swap to the v 1b input occurs. v 1a remains the active input. v 1b v 1n v 1a agnd filter and compare to multiplier fault a b v 1a v 1b v 1b < 93.75% of v 1a >0 <0 active point ? inactive input 6.25% of active input 05040-026 0v fault v 1a v 1b figure 28. fault conditio ns for active input grea ter than inactive input fault with inactive input greater than active input figure 29 illustrates another fault condition. if the difference between v 1b , the inactive input, and v 1a , the active input (that is, being used for billing), becomes greater than 6.25% of v 1b , the fault indicator becomes active and a swap over to the v 1b input occurs. the analog input v 1b becomes the active input. again, a time constant of about 3 sec is associated with this swap. v 1a does not swap back to the active channel until v 1a is greater than v 1b and the difference between v 1a and v 1b in this orderbecomes greater than 6.25% of v 1a . however, the fault indicator becomes inactive as soon as v 1a is within 6.25% of v 1b . this threshold eliminates potential chatter between v 1a and v 1b . v 1b v 1n v 1a agnd filter and compare to multiplier fault a b v 1a v 1b v 1a < 93.75% of v 1b >0 <0 active point ? inactive input 6.25% of inactive input 05040-027 0v fault + swap v 1a v 1b figure 29. fault conditions for inacti ve input greater than active input calibration concerns typically, when a meter is being calibrated, the voltage and current circuits are separated, as shown in figure 30 . this means that current passes through only the phase or neutral circuit. figure 30 shows current being passed through the phase circuit. this is the preferred option because the ADE7761A starts billing on the input v 1a on power-up. the phase circuit ct is connected to v 1a in figure 30 . because there is no current in the neutral circuit, the fault indicator comes on under these conditions. however, this does not affect the accuracy of the calibration and can be used as a means to test the functionality of the fault detection. agnd v 1b v 1n v 1a r f r f c f c f ct ct rb rb 0v v 1a ib ib phase neutral 1 rb + vr = rf. vr 1 rb 1 ra 1 v 2p r f v 2n c t c f v test current 240v rms 05040-028 figure 30. conditions for calibration of channel b if the neutral circuit is chosen for the current circuit in the arrangement shown in figure 30 , this may have implications for the calibration accuracy. the ADE7761A powers up with the v 1a input active as normal. however, because there is no current in the phase circuit, the signal on v 1a is zero. this causes a fault to be flagged and the active input to be swapped to v 1b (neutral). the meter can be calibrated in this mode, but the phase and neutral cts may differ slightly. because under no-fault conditions all billing is carried out using the phase ct, the meter should be calibrated using the phase circuit. of course, both phase and neutral circuits can be calibrated. missing neutral mode the ADE7761A integrates a novel fault detection that warns and allows the ADE7761A to continue to bill in case a meter is connected to only one wire (see figure 31 ). for correct operation of the ADE7761A in this mode, the v dd pin of the ADE7761A must be maintained within the specified range (5 v 5%). the missing neutral detection algorithm is designed to work over a line frequency of 45 hz to 55 hz.
ADE7761A rev. 0 | page 19 of 24 v 1b v 1n v 1a r f r f c f c f ct ct rb rb 0v v 1a 1 rb + vr = rf. vr 1 rb 1 ra 1 v 2p r f v 2n c t c f 05040-029 load 244v rms power generator ib figure 31. missing neutral system diagram the ADE7761A detects a missing neutral condition by continuously monitoring the voltage channel input (v 2p ? v 2n ). the fault pin is held high when a missing neutral condition is detected. in this mode, the ADE7761A continues to bill the energy based on the signal level on the current channel (see figure 32 ). the billing rate or frequency outputs can be adjusted by changing the dc level on the miscal pin. v 1a v 1n v 1b missing neutral gain adjusmtent digital-to- frequency converters cf f1 f2 05040-030 zero crossing detection a > b b > a b <> a adc adc adc miscal lpf hpf figure 32. energy calculation in missing neutral mode important note for billing of active energy the ADE7761A provides pulse outputscf, f1, and f2 intended to be used for the billing of active energy. pulses are generated at these outputs in two different situations. case 1 : when the analog input v 2p C v 2n complies with the conditions described in figure 34 , cf, f1, and f2 frequencies are proportional to active power and can be used to bill active energy. case 2 : when the analog input v 2p C v 2n does not comply with the conditions described in figure 34 , the ADE7761A does not measure active energy but a quantity proportional to kah. this quantity is used to generate pulses on the same cf, f1, and f2. this situation is indicated when the fault pin is high. analog devices, inc. cautions users of the ADE7761A about the following: ? billing active energy in case 1 is consistent with the understanding of the quantity represented by pulses on cf, f1, and f2 outputs (watt-hour). ? billing active energy while th e ADE7761A is in case 2 must be decided knowing that the entity measured by the ADE7761A in this case is ampere-hour and not watt-hour. users should be aware of this limitation and decide if the ADE7761A is appropriate for their application. missing neutral detection the ADE7761A continuously monitors the voltage input and detects a missing neutral condition when the voltage input peak value is smaller than 9% of the an alog full scale or when no zero crossings are detected on this input (see figure 33 ). 0v fs fs 0v fs 05040-031 9% of fs 0v filter and threshold v2 v 2p v 2n agnd adc missing neutral |v2| peak < 9% of full scale v 2p ?v 2n v 2p ?v 2n v 2p ? v 2n no zero crossing on v2 or figure 33. missing neutral detection the ADE7761A leaves the missing neutral mode for normal operation when both conditions are no longer valid, that is, a voltage peak value of greater than 9% of full scale and zero crossing on the voltage channel is detected (see figure 34 ). 05040-032 filter and threshold v2 v 2p v 2n a gnd adc missing neutral |v2| peak > 9% of full scale and zero crossing on v2 fs +9% of fs ?9% of fs v 2p ? v 2n figure 34. return to normal mode after missing neutral detection
ADE7761A rev. 0 | page 20 of 24 missing neutral gain calibration example when the ADE7761A is in missing neutral mode, the energy is bill based on the active current input signal level. the frequency outputs in this mode can be calibrated with the miscal analog input pin. in this mode, applying a dc voltage of 330 mv on miscal is equivalent to applying, in normal mode, a pure sine wave on the voltage input with a peak value of 330 mv. the miscal input can vary from 0 v to 660 mv (see the analog inputs section). when set to 0 v, the frequency outputs are close to zero. when set to 660 mv dc, the frequency outputs are twice that when miscal is at 330 mv dc. in other words, equation 7 can be used in missing neutral mode by replacing v2 rms by miscal rms /2. in normal mode, ac voltages of 330 mv peak are applied to v1 and v2, and then the expected output frequency on f 1 and f 2 is calculated as: gain =1 ; pga =0 f 1C4 = 1.7 hz, scf = s1 = s0 = 0 v1 = rms of 330 mv peak ac = 0.33/2 v v2 = rms of 330 mv peak ac = 0.33/2 v v ref = 2.5 v (nominal reference value) hz084.0 5.222 hz7.133.033.070.5 , 2 21 = = frequency ff 2 41 21 2/ 1 70.5 , ref rms rms v f miscal vgain frequenc y f f ? = (8) cf frequency = f 1 ? f 2 frequency 64 = 5.4 hz in missing neutral mode, the ac voltage of 330 mv peak is applied to v1, no signal is connected on v2, and a 330 mv dc input is applied to miscal. with the ADE7761A in the same configuration as the previous example, the expected output frequencies on cf, f 1 , and f 2 are where: f 1 , f 2 frequency is the output frequency on f 1 and f 2 (hz). v1 rms is the differential rms voltage signal on channel 1 (v). miscal rms is the differential rms voltage signal on the miscal pin (v). hz084.0 5.22 hz7.12/33.033.070.5 , 2 = = frequency ff 21 gain is 1 or 16, depending on the pga gain selection made using logic input pga. cf frequency = f 1 , f 2 frequency 64 = 5.4 hz v ref is the reference voltage (2.5 v 8%) (v). f 1-4 is one of four possible frequencies selected by using the logic inputs s0 and s1 (see tabl e 6 ).
ADE7761A rev. 0 | page 21 of 24 applications interfacing to a microcontroller for energy measurement the easiest way to interface the ADE7761A to a microcontroller is to use the cf high frequency output with the output frequency scaling set to 2048 f1, f2. this is done by setting scf = 0 and s0 = s1 = 1 (see table 8 ). with full-scale ac signals on the analog inputs, the output frequency on cf is approximately 5.5 khz. figure 35 illustrates one scheme that could be used to digitize the output frequency and carry out the necessary averaging mentioned in the frequency output cf section. time 10% average frequency cf frequency ripple mcu up/down counter logic cf revp 1 ADE7761A fault 2 05040-033 1 revp must be used if the meter is bidirectional or direction of energy flow is needed. 2 fault must be used to record energy in fault condition. figure 35. interfacing the ADE7761A to an mcu as shown in figure 35 the frequency output cf is connected to an mcu counter or port, which counts the number of pulses in a given integration time, determined by an mcu internal timer. the average power, proportional to the average frequency, is time r counter power active average frequency average = = the energy consumed during an integration period is counter time time counter time power average energy = = = for the purpose of calibration, this integration time could be 10 sec to 20 sec to accumulate enough pulses to ensure correct averaging of the frequency. in normal operation, the integration time could be reduced to 1 sec or 2 sec depending on, for example, the required update rate of a display. with shorter integration times on the mcu, the amount of energy in each update may still have a small amount of ripple, even under steady load conditions. however, over a minute or more, the measured energy has no ripple. selecting a frequency for an energy meter application as shown in table 6 , the user can select one of four frequencies. this frequency selection determines the maximum frequency on f1 and f2. these outputs are intended to be used to drive the energy register (electromechanical or other). because only four different output frequencies can be selected, the available frequency selection was optimized for a meter constant of 100 impulses/kwh with a maximum current of between 10 a and 120 a. tabl e 9 shows the output frequency for several maximum currents (i max ) with a line voltage of 240 v. in all cases, the meter constant is 100 impulses/kwh. table 9. f1 and f2 frequency at 100 impulses/kwh i max (a) f1 and f2 (hz) 12.5 0.083 25 0.166 40 0.266 60 0.4 80 0.533 120 0.8 the f 1C4 frequencies allow complete coverage of this range of output frequencies on f1 and f2. when designing an energy meter, the nominal design voltage on channel 2 (voltage) should be set to half-scale to allow for calibration of the meter constant. the current channel should also be no more than half- scale when the meter sees maximum load, which accommodates overcurrent signals and signals with high crest factors. table 1 0 shows the output frequency on f1 and f2 when both analog inputs are half-scale. the frequencies listed in table 10 align well with those listed in table 9 for maximum load. table 10. f1 and f2 frequency with half-scale ac inputs s0 s1 f 1C4 (hz) frequency on f1 and f2, ch 1 and ch 2, half-scale ac inputs (hz) 0 0 1.72 0.085 0 1 3.44 0.17 1 0 6.86 0.34 1 1 13.5 0.68 when selecting a suitable f 1C4 frequency for a meter design, the frequency output at i max (maximum load) with a meter constant of 100 impulses/kwh should be compared with column 4 of table 10 . the frequency that is closest in table 10 determines the best choice of frequency (f 1-4 ). for example, if a meter with a maximum current of 40 a is being designed, the output frequency on f1 and f2 with a meter constant of 100 impulses per kwh is 0.266 hz at 40 a and 240 v (see table 9 ).
ADE7761A rev. 0 | page 22 of 24 looking at tabl e 10 , the closest frequency to 0.266 hz in column 4 is 0.17 hz. therefore, f2 (3.4 hz; see tabl e 6 ) is selected for this design. frequency outputs figure 2 is a timing diagram for the various frequency outputs. the high frequency cf output is intended for communication and calibration purposes. cf produces a 90 ms wide, active high pulse (t 4 ) at a frequency that is proportional to active power. the cf output frequencies are given in table 8 . as with f1 and f2, if the period of cf (t 5 ) falls below 180 ms, the cf pulse width is set to half the period. for example, if the cf frequency is 20 hz, the cf pulse width is 25 ms. no-load threshold the ADE7761A includes a no-load threshold and start-up current feature that eliminates creep effects in the meter. the ADE7761A is designed to issue a minimum output frequency. any load generating a frequency lower than this minimum frequency does not cause a pulse to be issued on f1, f2, or cf. the minimum output frequency is given as 0.0045% of the full- scale output frequency. (see table 8 for maximum output frequencies for ac signals). for example, an energy meter with a meter constant of 100 impulses per kwh on f1, f2 using scf = 1, s1 = 0, and s0 = 1, the maximum output frequency at f1 or f2 is 0.68 hz and 43.52 hz on cf. the minimum output frequency at f1 or f2 is 0.0045% of 0.68 hz or 3.06 10 C5 hz. this is 1.96 10 C3 hz at cf (64 f1 hz). in this example, the no-load threshold is equivalent to 1.1 w of load or a startup current of 4.6 ma at 240 v. compare this value to the iec 32053-21 specification, which states that the meter must start up with a load equal to or less than 0.4% of i b . for a 5 a (i b b b ) meter, 0.4% of i b is equivalent to 20 ma. b note that the no-load threshold is not enabled when using the high cf frequency mode: scf = 0, s1 = s0 = 1. negative power information the ADE7761A detects when the current and voltage channels have a phase shift greater than 90 . this mechanism can detect a wrong connection of the meter or the generation of negative power. the revp pin output goes active high when negative power is detected and active low when positive power is detected. the revp pin output changes state as a pulse is issued on cf.
ADE7761A rev. 0 | page 23 of 24 outline dimensions compliant to jedec standards mo-150-ae 060106-a 20 11 10 1 7.50 7.20 6.90 8.20 7.80 7.40 5.60 5.30 5.00 seating plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarity 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 36. 20-lead shrink small outline package [ssop] (rs-20) dimensions shown in millimeters ordering guide model temperature range package description package option ADE7761Aars C40c to +85c 20-lead shri nk small outline package (ssop) rs-20 ADE7761Aars-rl C40c to +85c 20-lead shri nk small outline package (ssop) rs-20 ADE7761Aarsz 1 C40c to +85c 20-lead shrink small outline package (ssop) rs-20 ADE7761Aarsz-rl 1 C40c to +85c 20-lead shrink small outline package (ssop) rs-20 ADE7761Aars-ref reference board 1 z = pb-free part.
ADE7761A rev. 0 | page 24 of 24 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05040-0-7/06(0)

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